With the rapid development of the ultra-large-scale integration (VLSI), the manufacturing process of integrated circuits (ICs) has become more and more complex, and more and more precise. In order to improve the integration level and lower the production cost, the critical dimension (CD) of semiconductor devices has become smaller and smaller; while the quantity of the semiconductor devices in a unit area has been continuously increased. When continuously decreasing the critical dimension of the semiconductor devices, the geometries of the semiconductor devices have also been changed.
For a semiconductor device, when the channel length is shrunk to a scale comparable to the total width of the depletion regions at both sides of the gate structure, for example, the channel length may be in proximity to the total width of the depletion regions, some phenomena which are significantly different from the phenomena that happen to a semiconductor device having a relatively long channel region may occur. Under this circumstance, the performance of the semiconductor device is significantly affected; and the effects caused by reducing the channel length are referred as short channel effects (SCEs).
The SCEs increase the drive current of the semiconductor devices, but the offset current, i.e., an absolute value of the difference between input currents of the semiconductor devices, may deteriorate the performance of the semiconductor devices. For example, a source to drain punch may happen. Further, the function of the semiconductor devices may also become more and more complex. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.